SNR ENGINEER, PD SG CMP
Core
Develop and optimize Chemical Mechanical Planarization (CMP) processes for next-generation 3D NAND nodes, transferring them to high-volume manufacturing and improving process margins.
Role type
Senior IC process development engineer (semiconductor manufacturing)
Builds
3D NAND memory chips and storage solutions
Domain
Semiconductor manufacturing / Materials Science
Required skills
CMP process characterization, Design of Experiments (DoE), failure analysis, FMEA, 8D methodology, SPC/FDC, data analysis (Y3), consumables development, hardware evaluation
Preferred skills
AI-driven workflow optimization, patent generation, multi-functional project leadership
Technologies
AMAT, EBARA, Y3, CMP equipment
Responsibilities
Characterize and develop CMP processes for 3D NAND; transfer processes to high-volume manufacturing; resolve assembly process issues using failure analysis; manage experiments to widen process margins; implement advanced process monitoring and control methodologies; lead multi-functional projects for yield and cost improvement.
Seniority
Senior, hands-on IC