HVM PEE Dry Etch MTS/SMTS
Core
Lead the development, characterization, and optimization of Dry Etch processes for advanced DRAM structures.
Role type
Senior IC semiconductor process engineer (dry etch)
Builds
Advanced DRAM memory and storage solutions
Domain
Semiconductor manufacturing / Memory technology
Required skills
Dry etch process development, Plasma etch mechanisms, Process control, Defect mitigation, Cross-functional team leadership, Root cause analysis, Technical roadmap definition, Equipment vendor management
Preferred skills
High aspect ratio etching, Critical dimension control, Selectivity challenges, Data analytics, DOE methodologies, SPC tools, Sub-20nm integration challenges
Technologies
Lam, TEL, AMAT
Responsibilities
Lead development and optimization of Dry Etch processes for advanced DRAM structures, Collaborate cross-functionally with integration, metrology, equipment, and R&D teams, Define and execute technical roadmaps aligned with DRAM scaling requirements, Evaluate and implement new etch technologies and hardware platforms, Mentor junior engineers, Interface with equipment vendors to co-develop solutions, Drive root cause analysis and continuous improvement initiatives
Seniority
Senior, hands-on IC