Principal Place and Route Engineer
Core
Develop partitioning, placement, and routing algorithms for hardware resources, tune results for LLM inference workloads, and model new hardware constraints in solvers.
Role type
Principal IC place-and-route algorithm engineer
Builds
Place-and-route solvers and heuristics for chip architectures
Domain
Hardware compilation and optimization for AI/LLM inference
Deliverable
production ML models
Required skills
graph algorithms, partitioning algorithms, combinatorial optimization, MILP solvers, C/C++, Python, large parallel system design, NP-hard problem solving
Preferred skills
FPGA/CGRA place-and-route, ML compilers (MLIR, LLVM, TVM, XLA), SAT/SMT solvers, LLM inference stacks (vLLM, PyTorch)
Technologies
C, C++, Python, MLIR, LLVM, TVM, XLA, vLLM, PyTorch
Responsibilities
Develop partitioning, placement, and routing algorithms; Tune place-and-route results for target workloads; Model new hardware constraints in solvers; Analyze compiled output with performance engineers; Build infrastructure for prototyping and regression testing
Seniority
Principal, hands-on IC
