TIM Wastewater & DIW Engineer
Core
Central engineering role driving technical standardization, reliability roadmaps, and new technology deployment for semiconductor wafer fab water utility systems (DIW/UPW, wastewater, reclaim) across TI Asia sites.
Role type
Senior IC water utility systems engineer (semiconductor)
Builds
Utility systems for semiconductor wafer fabs (DIW/UPW, STP, IWW, reclaim/reuse)
Domain
Semiconductor manufacturing / Water treatment engineering
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
Semiconductor utility systems engineering, DIW/UPW systems, industrial wastewater treatment, water reclaim/reuse technologies, capital project leadership, cross-site standardization, reliability engineering (FMEA), root cause analysis, new technology evaluation & deployment, PLC/SCADA optimization, water chemistry, system capacity assessment
Preferred skills
Leading capital/expense projects, full water lifecycle technology expertise (RO, EDI, UV, UF), advanced water chemistry, systemic cross-site problem solving, technical benchmarking, pilot testing, enterprise best practice development, centralized engineering organization experience
Technologies
RO, EDI, UF, UV, PLC, SCADA, Mixed Bed, Ion Exchange, STP, CVD
Responsibilities
Develop long-term discipline reliability roadmaps and mitigate systemic risks; Serve as central SME for advanced troubleshooting of water systems; Lead full-lifecycle delivery of capital and expense engineering projects; Conduct technical benchmarking and feasibility studies for new water treatment technologies; Establish system performance dashboards to drive continuous reliability improvement; Mentor junior engineers and elevate discipline technical competency
Seniority
Senior, hands-on IC with strategic cross-site impact
