TIONE-高级推理研发工程师-上海/杭州/深圳/北京
Core
Lead performance engineering and architecture for ultra-large-scale LLM inference systems, optimizing frameworks like vLLM/TensorRT-LLM and implementing low-bit quantization and MoE scheduling.
Role type
Senior IC machine-learning engineer (LLM inference systems)
Builds
Production-grade LLM inference engines and optimized AI chip platforms
Domain
Artificial Intelligence / Large Language Models / High-Performance Computing
Deliverable
production ML models
Required skills
LLM inference system architecture, vLLM/TensorRT-LLM kernel optimization, low-bit quantization (INT4/FP8/AWQ), MoE distributed scheduling, heterogeneous compute adaptation, GPU/NPU hardware optimization, datacenter networking (RDMA/RoCE)
Preferred skills
None stated
Technologies
vLLM, TensorRT-LLM, LightLLM, Ascend, Hygon, Tianheng, HCCL, NCCL, HGX, A100, H800, L20
Responsibilities
Lead performance engineering for trillion-parameter LLMs; Implement low-bit quantization and MoE optimization; Design unified multi-modal inference architecture; Adapt inference engines to AI chips; Optimize core operators for GPU/NPU; Oversee overseas datacenter GPU and network acceptance.
Seniority
Senior, hands-on IC
