混元推理算子开发工程师
Core
Design, develop, and optimize core inference operators (Transformers, Convolution, Pooling) to enhance end-to-end model inference performance across heterogeneous hardware.
Role type
Senior IC inference operator engineer (LLM/CPU/GPU/NPU)
Builds
High-performance inference engines and optimized operator libraries for large language models
Domain
AI Infrastructure / Deep Learning / Heterogeneous Computing
Deliverable
production ML models
Required skills
C/C++ programming, CUDA kernel development, computer architecture (CPU/GPU cache, parallelism), deep learning framework internals (PyTorch/TensorFlow), quantization, operator fusion, dynamic batching, SIMD instruction sets (AVX2/AVX512), memory management, concurrency optimization
Preferred skills
LLaMA/GPT/BERT inference optimization, TensorRT, cuDNN/cuBLAS, OpenMP, BLAS/LAPACK, Ascend/Cambricon chip development, vLLM, Triton
Technologies
CUDA, TensorRT, PyTorch, TensorFlow, C++, C, OpenMP, AVX2, AVX512, cuDNN, cuBLAS, vLLM, TensorRT-LLM, Triton, Ascend, Cambricon
Responsibilities
Design and optimize inference operators for Transformer series, convolution, and pooling; adapt and optimize operators for CPU, GPU, and NPU platforms; design inference engine architecture and scheduling strategies; research and implement frontier optimization techniques (quantization, sparsity, fusion); collaborate with algorithm and architecture teams; perform performance testing, debugging, and tuning.
Seniority
Senior, hands-on IC
