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Hardware Engineer (onsite) - 2010267

San Jose, California, US💼 Full-time🗓 2026-05-07 → 2026-07-31

Core

Lead the design, automation, and validation of System Level Tests (SLT) for High Volume Manufacturing of complex, high-power, high-speed System-on-Chips (SOCs).

Role type

Senior IC hardware test engineer (system-level test & automation)

Builds

Automated test flows, scripts, and hardware integration solutions for HVM of SOCs

Domain

Semiconductor manufacturing, high-power high-speed SoC production testing

Deliverable

production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work

Required skills

System-level test development, test automation, hardware integration (PCB, sockets, temperature control), yield analysis, NPI/HVM/RMA processes, scripting (Python, Perl)

Preferred skills

OSAT collaboration, silicon qualification, reliability testing (HTOL, Burn-in)

Technologies

Python, Perl, PCB design tools, test controllers, temperature control systems

Responsibilities

Design and validate SLT solutions for HVM, develop automated test flows and scripts, partner with architecture and design teams, optimize test coverage and performance, oversee hardware integration and handler selection, improve yield and reliability across NPI/HVM/RMA, collaborate with OSATs on production enablement, support silicon qualification and reliability testing

Seniority

Senior, hands-on IC

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